This technical article explores the implementation of a high-speed data acquisition system using a domestic FPGA (EG4S20). It covers the integration of a gigabit Ethernet TCP/IP stack, an 8-channel 1 MSPS ADC (AD7606C), and SDRAM for data buffering. The design also includes a Python-based host application for data visualization and control. The author provides a step-by-step approach to hardware-software co-design, addressing challenges such as clock domain crossing and data flow management. This is a valuable reference for engineers working on embedded systems, particularly those interested in FPGA-based networking and real-time data processing. The article emphasizes practical implementation details, making it a useful resource for both learning and production environments.
A detailed guide on using a domestic FPGA to implement gigabit Ethernet TCP/IP with an 8-channel ADC and SDRAM buffering, including a Python host interface.